Analysis and Test of the Effects of Single Event Upsets in the Configuration Memory of SRAM-based FPGAs

Day - Time: 05 April 2013, h.10:00
Place: Area della Ricerca CNR di Pisa - Room: C-29

Luca Maria Cassano

SRAM-based FPGAs are increasingly relevant in a growing number ofsafety-criticalapplication fields, ranging from automotive to aerospace. Theseapplication fields arecharacterized by a harsh radiation environment that can cause theoccurrence of SingleEvent Upsets (SEUs) in digital devices. Designing safety-criticalapplicationsrequires accurate methodologies to evaluate the system?s sensitivity toSEUsas early as possible during the design process. Moreover it is necessaryto detect theoccurrence of SEUs during the system life-time.In this talk we present a set of software tools that could be used bydesigners ofSRAM-based FPGA safety-critical applications to assess the sensitivity toSEUs of thesystem and to generate test patterns for in-service testing. Inparticular three tools have been designed and developed: (i) ASSESS:Accurate Simulator of SEuS affecting the configuration memory ofSRAM-based FPGAs; (ii) UA2TPG: Untestability Analyzerand Automatic Test Pattern Generator for SEUs Affecting the ConfigurationMemoryof SRAM-based FPGAs; and (iii) GABES: Genetic Algorithm Based Environmentfor SEU Testing in SRAM-FPGAs.